1. Field of the Invention
The invention relates generally to the design of integrated circuits and more particularly to systems and methods for providing delay budget assignments that meet circuit timing requirements.
2. Related Art
As digital devices (e.g., integrated circuits) have become more complex, including more and more electronic components, better tools are needed to design these devices. In particular, the efficiency of the tools is in need of improvement just to handle the ever increasing size of the design problems.
Part of the task of designing a digital device is to determine the timing for the device's circuits. The devices will only work properly if data and control signals are available when they are needed. For instance, circuitry that receives certain data at time t1 may have to process the data and generate a corresponding output signal by time t2 so that it can be used by another part of the device. A proposed design for the circuitry must therefore meet the timing constraint that the delay along a path through the circuitry is no more than t2-t1 (the delay budget.) The performance of the device may also be affected by the allocation of this delay budget to subcomponents of the circuitry along the path. Delay budget assignment is a very important part of integrated circuit design. It is performed to distribute the timing slack (extra time that is available) on a given timing path to the path components, such as interconnects, cells, nets, etc. This is done in such a way that all timing constraints (of which there are usually many) are satisfied.
Previously, this was accomplished using a methodology that required the computation of timing for every path through a given component and scaling the timing for the component according to the tightest timing constraint. Using this methodology, an initial delay was first assigned to each component in the circuit. Then, for each component, all the paths that included the component were determined. For each of these paths, it was necessary to determine the path delay (the sum of all the component delays in the path,) and the total budget (maximum delay) for the path. From these values, a scaling factor was determined. This scaling factor was equal to the smaller of: 1; or the budget divided by the current path delay. The component being considered therefore had multiple scaling factors (one for each delay path through the component) associated with it. The smallest of the scaling factors was chosen for the component, and the delay budget for the component was determined by taking the product of the selected scaling factor and the delay initially assigned to the component (or a minimum component delay, whichever was larger.)
As the complexity of the circuits grew, however, this methodology became increasingly expensive and impractical because of the required evaluation of each and every path through the circuit. The computational expense of this methodology led to the use of another methodology that replaced the exact computation of the smallest scaling factor with an approximation. Rather than computing the scaling factor for every path through the component, the scaling factor was approximated by dividing the smallest of the required path delays for all of the paths by the largest of the current path delays for all of the paths. Because the different paths through the component under consideration could have very different delays, this approximation could be very inaccurate. For instance, even if all of the paths already satisfied their timing constraints (i.e., the current path delay is less than or equal to the required path delay,) different overall delays in the paths would result in selection of a scaling factor less than 1 (implying that one or more of the paths violate the corresponding timing constraints.)
It would therefore be desirable to provide systems and methods for delay budget assignment that do not incur the computational expense of the first methodology, and do not suffer from the inaccuracies of the second methodology.